SENIOR STAFF EGINEER DIGITAL VERIFICATION
LinkedIn|As PowerUp|Thành Phố Cao Lãnh, Dong Thap, Vietnam|6 Aug 2026
JOB DESCRIPTION
In Your New Role You Will
- Be responsible for developing SystemVerilog – UVM testbench and solve potentially complex problems related to test bench development
- Debug failing test cases to root cause
- Be responsible for defining and writing a functional coverage model
- Participate in reviews to ensure test bench meets quality and is complete
- Contribute to verification perspective in Design and Concept meetings
- Ensure test bench meets sign-off targets, including coverage, functional safety and test bench qualification
- Develop deep understanding of complex IPs/SoCs and take end-to-end ownership of their verification
- Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology
- Proactively help increase efficiency of verification activities and mitigate risks early
- Contribute to enhancing Verification strategy and architecture of IP/SoC testbenches